1. Field of the Invention
The present invention relates to a pulse-based flip-flop.
2. Description of the Related Art
Flip-flops and latches may be used as data storage devices in integrated semiconductor circuits. A flip-flop may sample an input signal and convert the input signal into an output signal based upon an clock signal. A latch may differ from a flip-flop in its signal processing in that the latch may continuously sample an input signal and may convert the input signal into an output signal based on clock pulses that it may receive. FIG. 1 illustrates a block diagram of a conventional pulse-based flip-flop. The pulse-based flip-flop 100 may include of a latch 110 for converting input data DIN into output data DOUT in response to a first clock pulse signal and a second clock pulse signal ˜φ and φ generated by a pulse generator 120. The pulse-based flip-flop 100 may have an ideal operating speed and power consumption characteristics because the pulse-based flip flop may use a single latch 110 unlike a master-slave flip-flop, which may be constructed with two latches, a master latch and a slave latch, each of which may be composed of at least four gates. Referring to FIG. 2, the pulse generator 120 of the pulse-based flip-flop 100 may include three serially connected inverters, 122, 124, and 126. The first inverter 122, which may receive a clock signal CLOCK, an NAND gate 128, which may receive the clock signal CLOCK and an output signal of the third inverter 126, and may output a first clock pulse signal ˜φ. A fourth inverter 130, which may receive the output of the NAND gate 128, may output a second clock pulse signal φ. The delay time of the first, second, and third inverters, 122, 124 and 126, may determine the pulse widths of the first and second clock pulse signals ˜φ and φ.
However, the pulse generator 120 may have a large chip area and/or a higher power consumption than conventional latches which may be used in flip-flops because the pulse generator may be composed of more than four gates. The high power consumption and/or large chip area may not be ideal when a pulse-based flip-flop is used in a circuit with high-speed operation and/or low power consumption.